library ieee;
use ieee.std_logic_1164.all;

entity clock is
	generic(
		Period1 : Time := 1300 ps;
		Period0 : Time := 20 ns
	);
	port (
		enable: in bit;
		clock : out bit
	);
end entity clock;

architecture RTL of clock is
	
begin
	process
	variable clock_value: bit := '0';
	begin
		loop 
			if enable = '1' then
				clock <= '1';
				wait for Period1; 
				clock <= '0';
				wait for Period0;
			end if;
		end loop;
	end process;
end architecture RTL;
